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| author | Shaunak Saha <shaunak.saha@intel.com> | 2017-12-06 11:22:53 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-20 16:59:27 +0000 |
| commit | 41cfd5ba69783c33883d4515ffa15ac279afb831 (patch) | |
| tree | cd7c1eb29fd5c12341bcd7f9cb94cd1a5073efd5 /src/mainboard/amd | |
| parent | ac7b506181f94ff2f5974e0205f38d27368c3686 (diff) | |
soc/intel/apollolake: Add SMI and SCI support for ESPI
This patch adds the SMI bits for SMI_EN, SMI_STS and GPE
register in pm.h. The southbridge handler for espi smi is
also added. In gpe.h we add GPE0A_ESPI_SCI_STS which is
bit 20 in GPE register and enables the setting of the
ESPI_SCI STS bit to generate a wake event and/or an SCI/SMI.
TEST= Boot to OS.
Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22758
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/amd')
0 files changed, 0 insertions, 0 deletions