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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-07-17 10:35:00 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2019-07-18 11:46:50 +0000 |
| commit | 2c7d1848856ce7bd8539ed4af460a476c39ff2fb (patch) | |
| tree | 1034d2ac269307698ae5548b8f658c4833106173 /src/mainboard/amd/serengeti_cheetah_fam10 | |
| parent | 7815c074b4689d858fde7c8e02153c40de79645e (diff) | |
mb/siemens/{mc_apl1,...,mc_apl5}: Fix GPIO settings
Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.
Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah_fam10')
0 files changed, 0 insertions, 0 deletions