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authorFelix Held <felix-coreboot@felixheld.de>2020-07-20 15:46:56 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-07-23 13:46:40 +0000
commita19d98647b0b1862c28b362505b30f4551b2fe2c (patch)
tree48c2975b0cd46c5933156b9f334babf10d1bf8ff /src/mainboard/amd/mandolin/variants
parenta2b04f45c0f8383cf8d6f5ea513d1598c23e822c (diff)
vc/amd/fsp/picasso: add logical to lane number in port descriptor struct
The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/amd/mandolin/variants')
-rw-r--r--src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
index 326bcaa0e7..3625554a42 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
+++ b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
@@ -8,8 +8,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* MXM */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 8,
- .end_lane = 15,
+ .start_logical_lane = 8,
+ .end_logical_lane = 15,
.device_number = 1,
.function_number = 1,
.link_aspm = ASPM_L1,
@@ -21,8 +21,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* SSD */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 0,
- .end_lane = 1,
+ .start_logical_lane = 0,
+ .end_logical_lane = 1,
.device_number = 1,
.function_number = 7,
.link_aspm = ASPM_L1,
@@ -34,8 +34,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* WLAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 4,
- .end_lane = 4,
+ .start_logical_lane = 4,
+ .end_logical_lane = 4,
.device_number = 1,
.function_number = 2,
.link_aspm = ASPM_L1,
@@ -47,8 +47,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* LAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 5,
- .end_lane = 5,
+ .start_logical_lane = 5,
+ .end_logical_lane = 5,
.device_number = 1,
.function_number = 3,
.link_aspm = ASPM_L1,
@@ -60,8 +60,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* WWAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 6,
- .end_lane = 6,
+ .start_logical_lane = 6,
+ .end_logical_lane = 6,
.device_number = 1,
.function_number = 4,
.link_aspm = ASPM_L1,
@@ -73,8 +73,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* WIFI */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 7,
- .end_lane = 7,
+ .start_logical_lane = 7,
+ .end_logical_lane = 7,
.gpio_group_id = 1,
.device_number = 1,
.function_number = 5,
@@ -87,8 +87,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* SATA EXPRESS */
.port_present = true,
.engine_type = SATA_ENGINE,
- .start_lane = 2,
- .end_lane = 3,
+ .start_logical_lane = 2,
+ .end_logical_lane = 3,
.gpio_group_id = 1,
.channel_type = SATA_CHANNEL_LONG,
}
@@ -98,8 +98,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* MXM */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 8,
- .end_lane = 11,
+ .start_logical_lane = 8,
+ .end_logical_lane = 11,
.device_number = 1,
.function_number = 1,
.link_aspm = ASPM_L1,
@@ -111,8 +111,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* SSD */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 0,
- .end_lane = 1,
+ .start_logical_lane = 0,
+ .end_logical_lane = 1,
.device_number = 1,
.function_number = 7,
.link_aspm = ASPM_L1,
@@ -124,8 +124,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* WLAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 4,
- .end_lane = 4,
+ .start_logical_lane = 4,
+ .end_logical_lane = 4,
.device_number = 1,
.function_number = 2,
.link_aspm = ASPM_L1,
@@ -137,8 +137,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* LAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_lane = 5,
- .end_lane = 5,
+ .start_logical_lane = 5,
+ .end_logical_lane = 5,
.device_number = 1,
.function_number = 3,
.link_aspm = ASPM_L1,
@@ -150,8 +150,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* SATA */
.port_present = true,
.engine_type = SATA_ENGINE,
- .start_lane = 2,
- .end_lane = 3,
+ .start_logical_lane = 2,
+ .end_logical_lane = 3,
.gpio_group_id = 1,
.channel_type = SATA_CHANNEL_LONG,
}