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authorMartin Roth <martinroth@chromium.org>2021-08-12 12:45:16 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-08-30 18:54:40 +0000
commitce5813fdc5d527803ab560cec5e798a04b210d3e (patch)
tree32266925a97643a7c78010666b60f1165c31c0bf /src/mainboard/amd/mandolin/variants/cereme
parentfd078d85d01810a4f03a8c21d454c04d9e2d3ae4 (diff)
mb/(amd,google): Remove spi configuration from devicetree
Now that the SPI configuration has been moved into Kconfig, it is no longer needed in devicetree. BUG=b:194919326 TEST=Build & boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifdcd3f33173194c4a25794137756b143751edd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/amd/mandolin/variants/cereme')
-rw-r--r--src/mainboard/amd/mandolin/variants/cereme/devicetree.cb9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
index 628ba64725..dbb1a14d6d 100644
--- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
+++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
@@ -100,15 +100,6 @@ chip soc/amd/picasso
register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0"
register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0"
- # SPI Configuration
- register "common_config.spi_config" = "{
- .normal_speed = SPI_SPEED_33M, /* MHz */
- .fast_speed = SPI_SPEED_66M, /* MHz */
- .altio_speed = SPI_SPEED_33M, /* MHz */
- .tpm_speed = SPI_SPEED_33M, /* MHz */
- .read_mode = SPI_READ_MODE_QUAD114,
- }"
-
# eSPI Configuration
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN,