drop unsupported unfinished mainboard Advantech SOM GX DB533-C

Signed-off-by: Richard Smith <smithbone@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 0 insertions, 700 deletions

diff --git a/src/mainboard/advantech/som_gx533c/Config.lb b/src/mainboard/advantech/som_gx533c/Config.lb
deleted file mode 100644
index 556e3ccf14..0000000000
--- a/src/mainboard/advantech/som_gx533c/Config.lb
+++ /dev/null
@@ -1,143 +0,0 @@
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The linuxBIOS bootloader.
-##
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit linuxBIOS entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where linuxBIOS is entered)
-##
-if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of linuxBIOS startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx2
-  device pci_domain 0 on 
-    device pci 0.0 on end
-      chip southbridge/amd/cs5535
-        device pci 12.0 on
-        device pci 12.1 off end		# SMI
-        device pci 12.2 on  end		# IDE
-        device pci 12.3 off end 	# Audio
-        device pci 12.4 off end		# VGA
-      end
-    end
-  end
-
-  chip cpu/amd/model_gx2
-  end
-
-end
-
diff --git a/src/mainboard/advantech/som_gx533c/Options.lb b/src/mainboard/advantech/som_gx533c/Options.lb
deleted file mode 100644
index df3d1bdfb6..0000000000
--- a/src/mainboard/advantech/som_gx533c/Options.lb
+++ /dev/null
@@ -1,160 +0,0 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
-uses CONFIG_ROM_STREAM
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default HAVE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=0
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-
-default _RAMBASE = 0x00004000
-
-default CONFIG_ROM_STREAM     = 1
-
-##
-## The default compiler
-##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
-
-# Select the serial console base port
-default TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
-
diff --git a/src/mainboard/advantech/som_gx533c/auto.c b/src/mainboard/advantech/som_gx533c/auto.c
deleted file mode 100644
index 138ca720a3..0000000000
--- a/src/mainboard/advantech/som_gx533c/auto.c
+++ /dev/null
@@ -1,134 +0,0 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "superio/nsc/pc87360/pc87360_early_serial.c"
-#include "cpu/x86/bist.h"
-#include "cpu/x86/msr.h"
-#include <cpu/amd/gx2def.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e,  PC87360_SP1)
-
-#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
-#include "southbridge/amd/cs5535/cs5535_early_setup.c"
-#include "northbridge/amd/gx2/raminit.h"
-
-/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
-{
-	msr_t msr;
-	/* 1. Initialize GLMC registers base on SPD values,
-	 * Hard coded as XpressROM for now */
-	//print_debug("sdram_enable step 1\r\n");
-	msr = rdmsr(0x20000018);
-	msr.hi = 0x10075012;
-	msr.lo = 0x3900;
-	wrmsr(0x20000018, msr);
-
-	msr = rdmsr(0x20000019);
-	msr.hi = 0x18000008;
-	msr.lo = 0x696332a3;
-	wrmsr(0x20000019, msr);
-
-}
-
-#include "northbridge/amd/gx2/raminit.c"
-#include "sdram/generic_sdram.c"
-
-#define PLLMSRhi 0x00000226
-#define PLLMSRlo 0x00000008
-#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
-#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
-#include "northbridge/amd/gx2/pll_reset.c"
-
-
-static void msr_init(void)
-{
-	__builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
-
-	__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
-        __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
-        __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
-        __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
-        __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
-
-        __builtin_wrmsr(0x10000080, 0x3, 0x0);
-
-        __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
-        __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
-	__builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
-        __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
-        __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
-        __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
-
-
-        __builtin_wrmsr(0x50002001, 0x27, 0x0);
-        __builtin_wrmsr(0x4c002001, 0x1, 0x0);
-}
-
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller memctrl [] = {
-		{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
-	};
-	unsigned char temp;
-
-	msr_init();
-
-	pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	cs5535_early_setup();
-	print_err("done cs5535 early\n");
-	pll_reset();
-	print_err("done pll_reset\n");
-	/* Halt if there was a built in self test failure */
-	//report_bist_failure(bist);
-	
-	sdram_initialize(1, memctrl);
-
-	print_err("Done sdram_initialize\n");
-	print_err("Disable watchdog\n");
-	outb( 0x87, 0x4E);                            //enter SuperIO configuration mode
-	outb( 0x87, 0x4E);
-
-
-   	outb(0x20, 0x4e);
-	temp = inb(0x4f);
-	print_debug_hex8(temp);
-	if (temp != 0x52){
-		print_err("CAN NOT READ SUPERIO VID\n");
-	}
-
-	outb(0x29, 0x4e);
-	outb(0x7c, 0x4f);
-
-	outb( 0x07, 0x4E);                            //enable logical device 9
-	outb( 0x09, 0x4F);
-	outb(0x30, 0x4e);
-	outb(1, 0x4f);
-	outb( 0xF0, 0x4E);                            //set GP33 as outbut in configuration register F0h     Bit4 = \u20180\u2019
-	outb( 0xC7, 0x4F);
-	outb( 0xF1, 0x4E);                            //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
-	temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
-	print_debug_hex8(temp);print_debug(":");
-	temp = temp & ~8;
-	outb( temp, 0x4F);
-	temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
-	print_debug_hex8(temp);print_debug("\n");
-	/* Check all of memory */
-//	ram_check(0, 16384);
-//	ram_check(0x20000, 0x24000);
-//	ram_check(0x00000000, 640*1024);
-
-}
diff --git a/src/mainboard/advantech/som_gx533c/chip.h b/src/mainboard/advantech/som_gx533c/chip.h
deleted file mode 100644
index 45e8068522..0000000000
--- a/src/mainboard/advantech/som_gx533c/chip.h
+++ /dev/null
@@ -1,5 +0,0 @@
-extern struct chip_operations mainboard_advantech_som_gx533c_ops;
-
-struct mainboard_advantech_som_gx533c_config {
-	int nothing;
-};
diff --git a/src/mainboard/advantech/som_gx533c/cmos.layout b/src/mainboard/advantech/som_gx533c/cmos.layout
deleted file mode 100644
index 5ba4c032c1..0000000000
--- a/src/mainboard/advantech/som_gx533c/cmos.layout
+++ /dev/null
@@ -1,74 +0,0 @@
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-#96         288       r       0        temporary_filler
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-385          1       e       4        last_boot
-386          1       e       1        ECC_memory
-388          4       r       0        reboot_bits
-392          3       e       5        baud_rate
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-416          4       e       7        boot_first
-420          4       e       7        boot_second
-424          4       e       7        boot_third
-428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
-1008         16      h       0        check_sum
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Network
-7     1     HDD
-7     2     Floppy
-7     8     Fallback_Network
-7     9     Fallback_HDD
-7     10    Fallback_Floppy
-#7     3     ROM
-
-checksums
-
-checksum 392 1007 1008
-
-
diff --git a/src/mainboard/advantech/som_gx533c/debug.c b/src/mainboard/advantech/som_gx533c/debug.c
deleted file mode 100644
index 7eeabdef47..0000000000
--- a/src/mainboard/advantech/som_gx533c/debug.c
+++ /dev/null
@@ -1,66 +0,0 @@
-
-static void print_debug_pci_dev(unsigned dev)
-{
-	print_debug("PCI: ");
-	print_debug_hex8((dev >> 16) & 0xff);
-	print_debug_char(':');
-	print_debug_hex8((dev >> 11) & 0x1f);
-	print_debug_char('.');
-	print_debug_hex8((dev >> 8) & 7);
-}
-
-static void print_pci_devices(void)
-{
-	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
-		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
-			continue;
-		}
-		print_debug_pci_dev(dev);
-		print_debug("\r\n");
-	}
-}
-
-static void dump_pci_device(unsigned dev)
-{
-	int i;
-	print_debug_pci_dev(dev);
-	print_debug("\r\n");
-	
-	for(i = 0; i <= 255; i++) {
-		unsigned char val;
-		if ((i & 0x0f) == 0) {
-			print_debug_hex8(i);
-			print_debug_char(':');
-		}
-		val = pci_read_config8(dev, i);
-		print_debug_char(' ');
-		print_debug_hex8(val);
-		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
-		}
-	}
-}
-
-static void dump_pci_devices(void)
-{
-	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
-		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
-			continue;
-		}
-		dump_pci_device(dev);
-	}
-}
diff --git a/src/mainboard/advantech/som_gx533c/failover.c b/src/mainboard/advantech/som_gx533c/failover.c
deleted file mode 100644
index bdcb9eaed2..0000000000
--- a/src/mainboard/advantech/som_gx533c/failover.c
+++ /dev/null
@@ -1,32 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include "arch/romcc_io.h"
-#include "pc80/mc146818rtc_early.c"
-
-static unsigned long main(unsigned long bist)
-{
-	/* This is the primary cpu how should I boot? */
-	if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- cpu_reset:
-	asm volatile ("jmp __cpu_reset"
-		: /* outputs */ 
-		: "a"(bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
diff --git a/src/mainboard/advantech/som_gx533c/irq_tables.c b/src/mainboard/advantech/som_gx533c/irq_tables.c
deleted file mode 100644
index 636f129119..0000000000
--- a/src/mainboard/advantech/som_gx533c/irq_tables.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* This file was generated by getpir.c, do not modify! 
-   (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*2,	 /* there can be total 2 devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x12<<3)|0x0,   /* Where the interrupt router lies (dev) */
-	0x800,		 /* IRQs devoted exclusively to PCI usage */
-	0x1078,		 /* Vendor */
-	0x2,		 /* Device */
-	0,		 /* Crap (miniport) */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xdf,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
-		{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
-	}
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-        return copy_pirq_routing_table(addr);
-}
diff --git a/src/mainboard/advantech/som_gx533c/mainboard.c b/src/mainboard/advantech/som_gx533c/mainboard.c
deleted file mode 100644
index 31d03455b4..0000000000
--- a/src/mainboard/advantech/som_gx533c/mainboard.c
+++ /dev/null
@@ -1,12 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-#include "chip.h"
-
-struct chip_operations mainboard_advantech_som_gx533c_ops = {
-	CHIP_NAME("Advantech SOM GX DB533-C mainboard")
-};
-
diff --git a/src/mainboard/advantech/som_gx533c/reset.c b/src/mainboard/advantech/som_gx533c/reset.c
deleted file mode 100644
index 5796e17dc8..0000000000
--- a/src/mainboard/advantech/som_gx533c/reset.c
+++ /dev/null
@@ -1,43 +0,0 @@
-#if 0
-//#include "arch/romcc_io.h"
-#include <arch/io.h>
-
-typedef unsigned device_t;
-
-#define PCI_DEV(BUS, DEV, FN) ( \
-	(((BUS) & 0xFF) << 16) | \
-	(((DEV) & 0x1f) << 11) | \
-	(((FN)  & 0x7) << 8))
-
-static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
-{
-        unsigned addr;
-        addr = dev | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        outb(value, 0xCFC + (addr & 3));
-}
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
-{
-	unsigned addr;
-        addr = dev | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(device_t dev, unsigned where)
-{
-	unsigned addr;
-        addr = dev | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        return inl(0xCFC);
-}
-
-#include "../../../northbridge/amd/amdk8/reset_test.c"
-
-void hard_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
-}
-#endif