amd/geode_lx: Remove most boards

There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.

Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 0 insertions, 267 deletions

diff --git a/src/mainboard/aaeon/Kconfig b/src/mainboard/aaeon/Kconfig
deleted file mode 100644
index a60a4c5465..0000000000
--- a/src/mainboard/aaeon/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_AAEON
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/aaeon/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/aaeon/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "Aaeon"
-
-endif # VENDOR_AAEON
diff --git a/src/mainboard/aaeon/pfm-540i_revb/Kconfig b/src/mainboard/aaeon/pfm-540i_revb/Kconfig
deleted file mode 100644
index 6b156b2f30..0000000000
--- a/src/mainboard/aaeon/pfm-540i_revb/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-if BOARD_AAEON_PFM_540I_REVB
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_GEODE_LX
-	select NORTHBRIDGE_AMD_LX
-	select SOUTHBRIDGE_AMD_CS5536
-	select SUPERIO_SMSC_SMSCSUPERIO
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_1024
-	select POWER_BUTTON_FORCE_ENABLE
-
-config MAINBOARD_DIR
-	string
-	default aaeon/pfm-540i_revb
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "PFM-540I_REVB"
-
-config IRQ_SLOT_COUNT
-	int
-	default 4
-
-endif # BOARD_AAEON_PFM_540I_REVB
diff --git a/src/mainboard/aaeon/pfm-540i_revb/Kconfig.name b/src/mainboard/aaeon/pfm-540i_revb/Kconfig.name
deleted file mode 100644
index beaf0e72d3..0000000000
--- a/src/mainboard/aaeon/pfm-540i_revb/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AAEON_PFM_540I_REVB
-	bool "PFM-540I_REVB"
diff --git a/src/mainboard/aaeon/pfm-540i_revb/board_info.txt b/src/mainboard/aaeon/pfm-540i_revb/board_info.txt
deleted file mode 100644
index 76246af4f0..0000000000
--- a/src/mainboard/aaeon/pfm-540i_revb/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Board name: PFM-540I Rev.B
-Category: half
-Board URL: http://www.aaeonusa.com/products/details/?item_id=1043
diff --git a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
deleted file mode 100644
index f1f36938c7..0000000000
--- a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb
+++ /dev/null
@@ -1,73 +0,0 @@
-chip northbridge/amd/lx
-	device domain 0 on
-		device pci 1.0 on end				# Northbridge
-		device pci 1.1 on end				# Graphics
-		device pci 1.2 on end				# AES
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
-			register "lpc_serirq_enable" = "0x0000105a"
-			register "lpc_serirq_polarity" = "0x0000EFA5"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "1"	# 0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3E8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2E8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci c.0 on end			# ISA Bridge (PC104)
-			device pci e.0 on end			# Ethernet
-			device pci f.0 on			# ISA Bridge
-				chip superio/smsc/smscsuperio
-					device pnp 4e.0 off	# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 4e.3 on	# Parallel port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 4e.4 on	# Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.5 on	# Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 4e.7 on	# Keyboard
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 4e.a off end	# Runtime/ACPI
-
-					# superio/smsc/smscsuperio currently only supports the first 2 serial ports.
-					device pnp 4e.b off	# Com3
-						io 0x60 = 0x3e8
-						irq 0x70 = 10
-					end
-					device pnp 4e.c off	# Com4
-						io 0x60 = 0x2e8
-						irq 0x70 = 11
-					end
-				end
-			end
-			device pci f.2 on end			# IDE Controller
-			device pci f.4 on end			# OHCI
-			device pci f.5 on end			# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device cpu_cluster 0 on
-		chip cpu/amd/geode_lx
-			device lapic 0 on end
-		end
-	end
-end
diff --git a/src/mainboard/aaeon/pfm-540i_revb/irq_tables.c b/src/mainboard/aaeon/pfm-540i_revb/irq_tables.c
deleted file mode 100644
index 82aaa23ef4..0000000000
--- a/src/mainboard/aaeon/pfm-540i_revb/irq_tables.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Based on irq_tables.c from AMD's DB800 mainboard. */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 5
-#define PIRQB 11
-#define PIRQC 10
-#define PIRQD 9
-
-/* Map */
-#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA	 1		/* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB	 2		/* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC	 3		/* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD	 4		/* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,  /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,			/* Where the interrupt router lies (bus) */
-	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
-	0x00,			/* IRQs devoted exclusively to PCI usage */
-	0x100B,			/* Vendor */
-	0x002B,			/* Device */
-	0,			/* Miniport data */
-	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
-	0x00,			/* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-	  /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
-	  /* bus, dev|fn,           {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-	  /* CPU */
-	  {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-	  /* Ethernet */
-	  {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
-	  /* Chipset */
-	  {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
-	 }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
deleted file mode 100644
index 8ee2453419..0000000000
--- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Based on romstage.c from AMD's DB800 mainboard. */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include <spd.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <northbridge/amd/lx/raminit.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	if (device != DIMM0)
-		return 0xFF;	/* No DIMM1, don't even try. */
-
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-void asmlinkage mainboard_romstage_entry(unsigned long bist)
-{
-	static const struct mem_controller memctrl[] = {
-		{.channel0 = {DIMM0, DIMM1}}
-	};
-
-	SystemPreInit();
-	msr_init();
-
-	cs5536_early_setup();
-
-	/* Note: must do this AFTER the early_setup! It is counting on some
-	 * early MSR setup for CS5536.
-	 */
-	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	pll_reset();
-
-	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
-	sdram_initialize(1, memctrl);
-
-	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
-}