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authorWonkyu Kim <wonkyu.kim@intel.com>2020-01-08 11:51:37 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-01-25 10:42:58 +0000
commit591b0ff535d36f0f69e92c55fe465cbf70dcbfe4 (patch)
treeeeb0b9afd5eca479aa336afd6a0e3b05ca776b27 /src/lib/reset.c
parent6d126acfac7ec8c13f9814c98d1016c64545cabd (diff)
soc/intel/tigerlake: Configure ClkReq according to mainboard design
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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