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authorKapil Porwal <kapilporwal@google.com>2022-11-15 19:06:49 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-11-19 02:40:26 +0000
commit89ea31248e5ad2fc36cf1b31dcf041355af34c9c (patch)
treef944e342ef6e83a6706757fc9901fb646222ab96 /src/lib/memcpy.c
parent20c64a1210360adc880b8e4fdecc3bb2ae95fb59 (diff)
soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot
Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Port of commit 0e905801f8ff ("soc/intel: transition full control over PM Timer from FSP to coreboot"). NOTE: This will have a huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. BUG=none TEST=Boot to OS on google/rex. Excerpt from google/rex coreboot log: [SPEW ] EnableTcoTimer = 1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/lib/memcpy.c')
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