summaryrefslogtreecommitdiff
path: root/src/lib/memchr.c
diff options
context:
space:
mode:
authorKenji Chen <kenji.chen@intel.com>2014-10-10 03:08:15 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-02 22:27:49 +0200
commitb71d9b8a0f02d5f458620cb21cdfe7799b1faf84 (patch)
treecff61f8581b791b2247fd3137516a5cdd1ac38b4 /src/lib/memchr.c
parent1d84ef57c2f095e1b7fc63546860b018dfea1889 (diff)
Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:31424 TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 Reviewed-on: http://review.coreboot.org/9223 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/lib/memchr.c')
0 files changed, 0 insertions, 0 deletions