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| author | Marco Chen <marcochen@chromium.org> | 2020-05-28 13:54:39 +0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-29 18:33:05 +0000 |
| commit | 0c6abd786df61072f8dd2ec738bb05a5f8375775 (patch) | |
| tree | fd0f9c241facca8db6e918cb1048836a477994d2 /src/lib/coreboot_table.c | |
| parent | 44e683d6dd4a80426eb12e5e09579d9a05ee7077 (diff) | |
mb/google/dedede: add new SPD SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16
The first DRAM part supported by SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 is
NT6AP256T32AV-J2 so the SPD content is generally extracted from it's
SPD. On the other hand, SPD bytes 4 / 6 / 13 were amended to follow SoC's
requirement.
BUG=b:152277273
BRANCH=None
TEST=build the image successfully.
Change-Id: If6fb0855a961d1c68315a727466bf45569cf2597
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41813
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/lib/coreboot_table.c')
0 files changed, 0 insertions, 0 deletions