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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-12-08 21:16:43 -0700
committerSubrata Banik <subratabanik@google.com>2021-12-22 18:14:47 +0000
commita62cb5693b93a4bec3d4c0ae072d9622d6a5ea0f (patch)
tree687744b51c8fcae2f2b7ac6887c04cbcb9a411ef /src/include
parentd27dd97e17a8dfe4a9d8861cda51feabce809590 (diff)
device: Make pciexp_get_ltr_max_latencies a public function
Some device drivers may need to get access to the LTR values for their respective devices, therefore export this function instead of marking it static. BUG=b:204343849 Change-Id: Id372600e8adec0d55d3483726bb9353139685774 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pciexp.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index fbc769e7c6..756733e0d8 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -39,4 +39,6 @@ static inline bool pciexp_is_downstream_port(int type)
type == PCI_EXP_TYPE_PCIE_BRIDGE;
}
+bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop);
+
#endif /* DEVICE_PCIEXP_H */