diff options
| author | Furquan Shaikh <furquan@google.com> | 2015-06-10 20:43:24 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-17 11:56:12 +0200 |
| commit | 69139e0e2a55660d443e1a650ea0198361abe07b (patch) | |
| tree | d394cf47ea219ca042d68075231f58a4e6a1c700 /src/include | |
| parent | 2da9524aaf90b6b2f4d7fab81bfc82c9829e3d32 (diff) | |
coreboot_tables: Add CBMEM ID and tag for MTC
BUG=chrome-os-partner:41125
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: Ia95b2a21863df5c3d6c08e9a134618db03a58775
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8462a33c62ab34d0f5049fc3a7c5c2ee8e5e2e4c
Original-Change-Id: Ie48a9a776b1c3ad30acf924c3d073acc8f2a8eda
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276779
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10562
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/boot/coreboot_tables.h | 1 | ||||
| -rw-r--r-- | src/include/cbmem_id.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 35ebd6eb3c..c8d52517f9 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -229,6 +229,7 @@ struct lb_gpios { #define LB_TAB_VBOOT_HANDOFF 0x0020 #define LB_TAB_DMA 0x0022 #define LB_TAG_RAM_OOPS 0x0023 +#define LB_TAG_MTC 0x002b struct lb_range { uint32_t tag; uint32_t size; diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h index b9c5ff2d9b..1b0377075e 100644 --- a/src/include/cbmem_id.h +++ b/src/include/cbmem_id.h @@ -43,6 +43,7 @@ #define CBMEM_ID_MEMINFO 0x494D454D #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 +#define CBMEM_ID_MTC 0xcb31d31c #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_PIRQ 0x49525154 #define CBMEM_ID_POWER_STATE 0x50535454 @@ -88,6 +89,7 @@ { CBMEM_ID_MEMINFO, "MEM INFO " }, \ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ + { CBMEM_ID_MTC, "MTC " }, \ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ { CBMEM_ID_POWER_STATE, "POWER STATE" }, \ { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \ |