diff options
| author | V Sowmya <v.sowmya@intel.com> | 2018-01-23 14:44:45 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-01-25 16:12:46 +0000 |
| commit | 7c150472dff49d06c255d11e11c2363198bff928 (patch) | |
| tree | 3bc20550cd3f64922f778543b26def286fbab475 /src/include | |
| parent | cb8123ae487e80cd1f8d285d3833a1f96db9943c (diff) | |
soc/intel/skylake: Clean up the skylake PCH H device ID macros
Rename the device ID macros as per the skylake PCH H external design
specification.
Change-Id: I4e80d41380dc1973d02bc69ac32aad5c4741a976
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23381
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e84d86491b..612542d933 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2665,9 +2665,9 @@ #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48 #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM 0x9d46 -#define PCI_DEVICE_ID_INTEL_KBP_H_C236 0xa150 -#define PCI_DEVICE_ID_INTEL_KBP_H_PREMIUM 0xa14e -#define PCI_DEVICE_ID_INTEL_KBP_H_QM170 0xa14d +#define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150 +#define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e +#define PCI_DEVICE_ID_INTEL_SPT_H_QM170 0xa14d #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22 0x9d4b #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22 0x9d4e #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22 0x9d50 @@ -2770,7 +2770,7 @@ /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 -#define PCI_DEVICE_ID_INTEL_KBP_H_PMC 0xa121 +#define PCI_DEVICE_ID_INTEL_SPT_H_PMC 0xa121 #define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94 #define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194 #define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1 @@ -2809,9 +2809,9 @@ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 #define PCI_DEVICE_ID_INTEL_SPT_UART2 0x9d66 -#define PCI_DEVICE_ID_INTEL_KBP_H_UART0 0xa127 -#define PCI_DEVICE_ID_INTEL_KBP_H_UART1 0xa128 -#define PCI_DEVICE_ID_INTEL_KBP_H_UART2 0xa166 +#define PCI_DEVICE_ID_INTEL_SPT_H_UART0 0xa127 +#define PCI_DEVICE_ID_INTEL_SPT_H_UART1 0xa128 +#define PCI_DEVICE_ID_INTEL_SPT_H_UART2 0xa166 #define PCI_DEVICE_ID_INTEL_APL_UART0 0x5abc #define PCI_DEVICE_ID_INTEL_APL_UART1 0x5abe #define PCI_DEVICE_ID_INTEL_APL_UART2 0x5ac0 @@ -2889,7 +2889,7 @@ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 #define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8 #define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f -#define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa12f +#define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f #define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded /* Intel P2SB device Ids */ |