diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-05-19 15:59:55 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-21 11:23:12 +0000 |
| commit | dd4861ae04a7825f04470471fe56cc4fc46028dc (patch) | |
| tree | 55213b2f9d48c0543b66aad25af142cf70eebce9 /src/include | |
| parent | 7608ea0c9f6c8763bd80628adf2d977e60823275 (diff) | |
soc/intel/common: Add Alder Lake device IDs
Add Alder Lake specific Host and Graphics device IDs.
As per latest document number: 619501, these IDs got an update.
Change-Id: I548a903714ccc7470f1425ac67c0c66522437365
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54674
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 1a9aa35645..51e98aec1a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3813,6 +3813,8 @@ #define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_1 0x46b0 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_2 0x46a1 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_3 0x46a3 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 @@ -3909,7 +3911,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_S_ID_13 0x4673 #define PCI_DEVICE_ID_INTEL_ADL_S_ID_14 0x4623 #define PCI_DEVICE_ID_INTEL_ADL_S_ID_15 0x0060 -#define PCI_DEVICE_ID_INTEL_ADL_P_ID_1 0x4602 +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_1 0x4629 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_2 0x460a #define PCI_DEVICE_ID_INTEL_ADL_P_ID_3 0x4641 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_4 0x4649 @@ -3918,6 +3920,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_7 0x4601 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f +#define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 |