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authorWANG Siyuan <wangsiyuanbuaa@gmail.com>2015-05-20 14:41:01 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-06-13 02:22:49 +0200
commitf2dfef01e1fdf9d8218f0bc6ecfc3f943dc4d2a1 (patch)
tree3c0b66ab3395249ddfa4524ebc80bdf3007acc89 /src/include
parent597ee56261c75c4e621a83e5999bc84e772ed53f (diff)
southbridge/amd/pi: Add support for new AMD southbridge Kern
Kern is the southbridge of AMD Merlin Falcon(Carrizo). This add support of HD audio, lpc, sata and usb for Kern. Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10418 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a02a27c1aa..13e66db2ac 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -427,6 +427,13 @@
#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13 0x5A1E
#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21
+#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A
+#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E
+#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900
+#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901
+#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907
+#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908
+
#define PCI_VENDOR_ID_VLSI 0x1004
#define PCI_DEVICE_ID_VLSI_82C592 0x0005
#define PCI_DEVICE_ID_VLSI_82C593 0x0006