diff options
| author | Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> | 2021-04-22 05:00:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-26 08:28:22 +0000 |
| commit | 250e610fa082473b3592d06c69316ec1daa88116 (patch) | |
| tree | ecdded88b81b30c251520b9983ab4abc1df1fabb /src/include/spi_bitbang.h | |
| parent | b1e8a8a6cee3e67962ecb03afd84aabb391ff9a8 (diff) | |
vc/amd/fsp/cezanne:Add s0i_enable upd control
Add upd to enable S0i3 in fsp.
BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Cq-Depend: chrome-internal:3777391
Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/include/spi_bitbang.h')
0 files changed, 0 insertions, 0 deletions