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author | Nicholas Chin <nic.c3.14@gmail.com> | 2024-01-31 22:07:25 -0700 |
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committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-08-27 00:28:13 +0000 |
commit | 962152dcbfd46b249d8ea0ede287ebb78bd97d1e (patch) | |
tree | 0b42dfb52d011f7a91a90afcf8c307a1a0759176 /src/include/sar.h | |
parent | 8d900ae1bfe1def9b36d6393e1cbcc5dbd5bc350 (diff) |
mb/dell: Add Latitude E6520 (Sandy Bridge)
Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port. I was also sent the VBT binary, which was obtained
from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the
vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/include/sar.h')
0 files changed, 0 insertions, 0 deletions