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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-07-17 23:00:31 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-02 04:51:02 +0000
commit7369e83de1e42138245e728304dc743feaa08c32 (patch)
treef3b65393ed1f4c46f4abda8c5a23284bc43c792e /src/include/program_loading.h
parentfb32be4090f088da8db877d3dce42d95b50212b6 (diff)
AGESA: Add romstage timestamps
Experiments on f14 f15tn and 16kb suggest that TSC counter value shifts at end of raminit. To account for this all previously stored values in timestamp table are also divided by 4. Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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