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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-02 12:14:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:34:56 +0000 |
| commit | 35e76dde7708d0646c56eaf3b5c063b27d2add62 (patch) | |
| tree | 6ad9d075128f38187b3683c4951ff0a3911f3ebe /src/include/pc80 | |
| parent | efe3cfb476b39da5ece2583000e0f24b5daf560b (diff) | |
soc/intel/skylake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.
Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/pc80')
0 files changed, 0 insertions, 0 deletions