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authorBen Chan <benchan@chromium.org>2017-11-09 16:53:26 -0800
committerPatrick Georgi <pgeorgi@google.com>2017-11-10 09:49:18 +0000
commiteeb475c5c88b49fd14347ab558b784de8487567f (patch)
tree1c81e26891bcf18a2bd829259d8d3c9346976f50 /src/include/lib.h
parent6f1e8d24af98299c296b358e575b485300f851b9 (diff)
mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5
On Astronaunt, after the system enters the S5 power state, there is a 10-second timeout before the system transitions the power state from S5 to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78 on the APL platform, remains on during that period. If the system is powered back on before going to G3, the built-in modem won't go through a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted. Keeping the modem, and indirectly the SIM, powered during a quick system power cycle may sometimes be undesirable. For instance, we would like a SIM with PIN lock enabled to require unlocking each time the system is powered on. After the SIM receives a PIN, it may remain unlocked until its next power cycle. Also, it is often desirable to power cycle the modem when the system goes through a power cycle. For instance, a user may power cycle the system to recover a wedged modem. BUG=b:68365029 TEST=Tested the following on an Astronaunt device: 1. Verify that the modem is powered on after the system boots from cold. 2. Suspend the system to S0ix. Verify that the modem remains powered on when the system is in S0ix. After the system goes back to S0, verify that the SIM with PIN lock enabled doesn't request unlocking, and the modem can quickly reconnect to a network. 3. Configure the system to suspend to S3 instead of S0ix, and then repeat (2). 4. Perform a quick system power cycle, verify that the modem is powered cycle and the SIM with PIN lock enabled requests unlocking. Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2 Signed-off-by: Ben Chan <benchan@chromium.org> Reviewed-on: https://review.coreboot.org/22415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/include/lib.h')
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