diff options
| author | Yuchi Chen <yuchi.chen@intel.com> | 2024-06-25 10:50:18 +0800 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2024-08-06 16:47:48 +0000 |
| commit | f61c136f8ab66e550bef0f6dda66fd2656608adb (patch) | |
| tree | 5af95d6a7dc482ff1b70793a884173a57ee8bff2 /src/include/device/pci_ids.h | |
| parent | 377b13335914c5d3a23ddfb8a8b600cd1f260ea9 (diff) | |
soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platform
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300,
P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0.
Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83314
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device/pci_ids.h')
| -rw-r--r-- | src/include/device/pci_ids.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8b2de41b8b..b721bb4df6 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3232,6 +3232,7 @@ #define PCI_DID_INTEL_PTL_U_H_ESPI_29 0xe31d #define PCI_DID_INTEL_PTL_U_H_ESPI_30 0xe31e #define PCI_DID_INTEL_PTL_U_H_ESPI_31 0xe31f +#define PCI_DID_INTEL_SNR_LPC 0x18dc /* Intel PCIE device ids */ #define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -4425,6 +4426,7 @@ #define PCI_DID_INTEL_PTL_U_ID_1 0xb000 #define PCI_DID_INTEL_PTL_H_ID_1 0xb001 #define PCI_DID_INTEL_PTL_H_ID_2 0xb002 +#define PCI_DID_INTEL_SNR_ID 0x09a2 /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 @@ -4502,6 +4504,7 @@ #define PCI_DID_INTEL_PTL_H_TCSS_XHCI 0xe431 #define PCI_DID_INTEL_PTL_U_H_XHCI 0xe37d #define PCI_DID_INTEL_PTL_U_H_TCSS_XHCI 0xe331 +#define PCI_DID_INTEL_SNR_XHCI 0x18d0 /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 @@ -4534,6 +4537,7 @@ #define PCI_DID_INTEL_PTL_H_P2SB2 0xe44c #define PCI_DID_INTEL_PTL_U_H_P2SB 0xe320 #define PCI_DID_INTEL_PTL_U_H_P2SB2 0xe34c +#define PCI_DID_INTEL_SNR_P2SB 0x18dd /* Intel SRAM device Ids */ #define PCI_DID_INTEL_APL_SRAM 0x5aec |