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authorArthur Heymans <arthur@aheymans.xyz>2024-04-29 10:04:59 +0200
committerJulius Werner <jwerner@chromium.org>2024-06-20 19:34:14 +0000
commit6ed0ba1e93f99edef7a62c3670b4ec61103e0ae9 (patch)
tree80d30a886c7a291adc9d3c4566886a4f8aa38ff2 /src/include/device/pci_ehci.h
parent71c90104438e453af6afa396e78e75e4f874a9e0 (diff)
cbfstool: Read XIP stage alignment requirements from ELF
On x86_64 romstage can contain page tables and a page table pointer which have an larger alignment requirement of 4096. Instead of hardcoding it, read if from the ELF phdrs. Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82102 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/include/device/pci_ehci.h')
0 files changed, 0 insertions, 0 deletions