diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-06 00:29:58 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:05:30 +0000 |
| commit | 11ff753407ee7fd1cb2da06f8bedc5ac40ebbd95 (patch) | |
| tree | 6ecbb219bf48422b94a9e6ccdc89ba87a9a1bf16 /src/include/cpu/amd | |
| parent | b39e93e56fdd2b11b8e7a12889472f144673d05a (diff) | |
soc/amd/common/block/cpu/noncar: add get_usable_physical_address_bits()
In case the secure memory encryption is enabled, some of the upper
usable address bits of the host can't be used any more. Bits 11..6 in
CPUID_EBX_MEM_ENCRYPT indicate how many of the address bits are taken
away from the usable address bits in the case the secure memory
encryption is enabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia810b0984972216095da2ad8f9c19e37684f2a2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75623
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/cpu/amd')
| -rw-r--r-- | src/include/cpu/amd/cpuid.h | 4 | ||||
| -rw-r--r-- | src/include/cpu/amd/mtrr.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/include/cpu/amd/cpuid.h b/src/include/cpu/amd/cpuid.h index b593562a09..81d008de77 100644 --- a/src/include/cpu/amd/cpuid.h +++ b/src/include/cpu/amd/cpuid.h @@ -121,4 +121,8 @@ #define CPUID_EBX_THREADS_SHIFT 8 #define CPUID_EBX_THREADS_MASK (0xff << CPUID_EBX_THREADS_SHIFT) +#define CPUID_EBX_MEM_ENCRYPT 0x8000001f +#define CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT 6 +#define CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK (0x3f << CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT) + #endif /* CPU_AMD_CPUID_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 04d775cade..32a7949b19 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -12,6 +12,7 @@ #define MTRR_WRITE_MEM (1 << 3) #define SYSCFG_MSR 0xC0010010 +#define SYSCFG_MSR_SMEE (1 << 23) #define SYSCFG_MSR_TOM2WB (1 << 22) #define SYSCFG_MSR_TOM2En (1 << 21) #define SYSCFG_MSR_MtrrVarDramEn (1 << 20) |