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authorDuncan Laurie <dlaurie@chromium.org>2012-01-09 22:05:18 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-30 17:56:10 +0200
commit7b67892be88e3f12de91314ca45a834b4c84c719 (patch)
treef7e2fadeb00c47a32adb451b81538c26280c16cc /src/include/cpu/amd
parent527fc74a83a7b0fdeebfeb9ddd5890f11f01c102 (diff)
Make MTRR min hole alignment 64MB
This affects the algorithm when determining when to transform a range into a larger range with a hole. It is needed when for when I switch on an 8MB TSEG and cause the memory maps to go crazy. Also add header defines for the SMRR. Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/include/cpu/amd')
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