summaryrefslogtreecommitdiff
path: root/src/include/console
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2021-05-05 19:34:07 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-05-12 06:15:45 +0000
commit38e4a2d4cf3398d56640b03371ff1bd08b30aff5 (patch)
tree43b08640f8c99c49f6722e5ea98585e5858e5544 /src/include/console
parent01ecb77ef64c8fdce5258dc75b7c4eaf1ed57cd0 (diff)
include/console: Fix duplicate entry of postcode 0x79
Change POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x6e to avoid duplicate entry. Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/include/console')
-rw-r--r--src/include/console/post_codes.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 677cd36545..9682e4db6c 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -105,6 +105,13 @@
#define POST_ENABLING_CACHE 0x60
/**
+ * \brief Pre call to RAM stage main()
+ *
+ * POSTed right before RAM stage main() is called from c_start.S
+ */
+#define POST_PRE_HARDWAREMAIN 0x6e
+
+/**
* \brief Before Device Probe
*
* Boot State Machine: bs_pre_device()
@@ -175,13 +182,6 @@
#define POST_BS_WRITE_TABLES 0x79
/**
- * \brief Pre call to RAM stage main()
- *
- * POSTed right before RAM stage main() is called from c_start.S
- */
-#define POST_PRE_HARDWAREMAIN 0x79
-
-/**
* \brief Load Payload
*
* Boot State Machine: bs_payload_load()