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authorBora Guvendik <bora.guvendik@intel.com>2022-07-19 13:50:41 -0700
committerFelix Held <felix-coreboot@felixheld.de>2022-09-09 10:43:01 +0000
commit323bddb1bdf53e5b871339868272cd7324856262 (patch)
treea8432cda3d379f521fb9a9418b8118430bae9099 /src/include/console/console.h
parent8754965db1d308a4e66e63fc85e39710f18f7f92 (diff)
mb/intel/adlrvp: Enable Cr50 TPM over SPI for adlrvp_rpl
Configure GPIO pins, add Kconfig options and enable TPM device in devicetree. Add H1 TPM IRQ GPIO pin in gpio.c BUG=none BRANCH=firmware-brya-14505.B Cq-Depend: chromium:3774914 TEST=Boot the image and check the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I1b4119373f69954d620dc09e637a7571312a5fc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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