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authorFelix Held <felix-coreboot@felixheld.de>2022-01-11 17:05:11 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-01-27 22:14:05 +0000
commit2f478b85caac41b1ba2ade33380b4273474c46a0 (patch)
tree8e6c4dc68ef96f7826c3759057ccce04b4d80c06 /src/include/console/console.h
parentcea684df9fb1c9fc5164d8a26986fb5215deead7 (diff)
soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTs
Compared to Cezanne there are 3 more UARTs controllers. The PCI interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't contain a PIRQ mapping for UART4. The reference code has a mapping for this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5. Since the I2C5 controller isn't owned by the x86 side and I didn't see any mapping of the I2C5 controller into the x86 MMIO space, this seems very plausible. Also add the corresponding fields to the ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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