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authorFurquan Shaikh <furquan@google.com>2020-05-09 13:10:30 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-12 20:04:15 +0000
commit08c524c0b7266fd9f51e0d412bdac2b4d14c09e0 (patch)
tree5d4b1a3c3e966b53193c36f5c1962647b22b6934 /src/include/cbmem.h
parent56875113b7472d806655c7871e013eecefba70c5 (diff)
soc/amd/common/block/spi: Add support for common SPI configuration
This change adds support for following SPI configuration functions to common block SPI driver and exposes them to be used by SoC: 1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM, enables prefetching, disables 4dw burst mode and sets SPI speed and mode. 2. fch_spi_config_modes(): This allows SoC to configure SPI speed and mode. It uses SPI settings from soc_amd_common_config to configure the speed and mode. These functions expect SoC to include soc_amd_common_config in SoC chip config and mainboard to configure these settings in device tree. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41248 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/cbmem.h')
0 files changed, 0 insertions, 0 deletions