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authorJulien Viard de Galbert <jviarddegalbert@online.net>2018-03-07 15:28:15 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-20 00:43:58 +0000
commitc28f0e08024296b72f95f3475ff14ef22ccec046 (patch)
tree44e92931cef1e3dfcc0d4110a6a64aff739d113f /src/ec
parent3065157da825ee2389e05875f78178957ee9dd75 (diff)
mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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