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authorMike Banon <mikebdp2@gmail.com>2020-08-15 10:30:19 +0300
committerPatrick Georgi <pgeorgi@google.com>2020-08-24 09:18:12 +0000
commit8b7bda40f140e3d849a91660d2c84a4c324c8901 (patch)
tree7349796f92e0f5864397fc74a79210b8d889e56d /src/ec/google
parentd2a00d7a1c7c93b9f149e1c2c8150c1114d1374d (diff)
nb/amd/agesa: define DDR3_SPD_SIZE as a common value
Move a size of DDR3 SPD memory (always 256 bytes) to a common define. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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