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authorUwe Poeche <uwe.poeche@siemens.com>2022-05-24 08:45:13 +0200
committerPaul Fagerburg <pfagerburg@chromium.org>2022-06-03 15:22:49 +0000
commit954af5293f3d72e8f389dff6f2a742f9fbdf56d7 (patch)
tree67b44924ce282fc8a43239a55cfeb9fd02b5d54c /src/ec/google/chromeec/ec.h
parent9b1fc309ed097852061cbff867fc15296841430c (diff)
soc/intel/elkhartlake: Select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR
Since of moving RAPL disabling to common code a config switch is available to select that RAPL disabling has to be done via MCHBAR. This patch selects the switch for EHL. Test: Boot mc_ehl1 and ensure that relevant bits in MCHBAR are the same as before the patch. Change-Id: I1d0b7f650aa3ccf89c5c35d9b60a83a1ce48c74f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/ec/google/chromeec/ec.h')
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