diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2023-06-23 09:48:36 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-03 13:34:01 +0000 |
| commit | 865180d681a6e3fcff8cfbf13614997256a728a4 (patch) | |
| tree | aedea311debd0ef70a8f41130ba1b8c2f66dfc5b /src/drivers | |
| parent | 00d71ffca8d6102326897edd6f6504284635201d (diff) | |
drivers/spi_flash: Always exit 4-byte address mode when memory-mapped
Always send the Exit 4-Byte Address Mode (E9h) command before the first
access to the SPI flash in all stages when the SPI flash is
memory-mapped. This is useful for x86 mainboards that do not access SPI
flash in bootblock yet still need to exit 4-byte addressing mode in
romstage or ramstage.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/spi/spi_flash.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 5182684478..7619f64364 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -18,6 +18,9 @@ #define ADDR_MOD 0 #endif +#define SPI_FLASH_EXIT_4BYTE_STAGE \ + (ENV_INITIAL_STAGE || CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) + static void spi_flash_addr(u32 addr, u8 *cmd) { /* cmd[0] is actual command */ @@ -548,8 +551,10 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash) CONFIG_ROM_SIZE); } - if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && ENV_INITIAL_STAGE) + if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && SPI_FLASH_EXIT_4BYTE_STAGE) { + printk(BIOS_DEBUG, "SF: Exiting 4-byte addressing mode\n"); spi_flash_cmd(&flash->spi, CMD_EXIT_4BYTE_ADDR_MODE, NULL, 0); + } return 0; } |