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authorSridhar Siricilla <sridhar.siricilla@intel.com>2022-04-28 23:32:01 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-11-21 14:04:24 +0000
commite5ca71db06a539d30f83d5fdf920e24ef4891df5 (patch)
tree4a2ce829c27efc766a068d6cd85d63d487799a9e /src/drivers/usb/ehci.h
parent88019ddbdf367ce8e44fd46d46ad042f9ca78355 (diff)
soc/intel/common: Add support to read CPU and PCH Trace Hub modes
The patch parses CPU and PCH Trace Hub modes from the debug area in the Descriptor Region. The modes can be updated in the debug area in order to configure the CPU and PCH Trace Hub modes. The debug area's offset starts from the SPI Flash offset:0xf00. For runtime debugging, the OEM Section in the Descriptor Region is being used as debug area. The OEM Section details are documented in the SPI Programmer Guide of CSE Lite kit. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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