summaryrefslogtreecommitdiff
path: root/src/drivers/siemens/nc_fpga
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-09-24 23:38:53 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2020-10-15 08:31:54 +0000
commit4b290b7b6f763f369b78cb83054e6ad65d83c4a3 (patch)
tree34f691a8b73a7864c0cb28b3309f265cf026b08e /src/drivers/siemens/nc_fpga
parent11334729c9aa3f09b3e01a491a2d007a0aea7201 (diff)
nb/intel/haswell: Account for DPR region in memory map
While MRC.bin does not allocate any memory for DPR by default, it can be patched to do so. However, the current northbridge code does not account for DPR and will, among other things, place CBMEM inside it. Even though this may seem like a good thing, it renders TianoCore unable to boot and clashes with Intel TXT support (the reason to enable DPR to begin with). Update memmap.c so that CBMEM top does not fall within DPR. Also, report DPR as reserved, so that OSes know that the DPR memory is not to be used. Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/drivers/siemens/nc_fpga')
0 files changed, 0 insertions, 0 deletions