diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-03 23:18:01 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-08 04:51:32 +0000 |
commit | 9970b61ad3049d87650cd7b4eb5f47d667098186 (patch) | |
tree | 912ee2624ebd4d9c68ab62cbde170c1e5d114b0f /src/drivers/intel | |
parent | 0a4457ff44b10f22b711f64e88888c757fbedf32 (diff) |
arch/x86: Move TSEG_STAGE_CACHE implementation
This is declared weak so that platforms that do not
have smm_subregion() can provide their own implementation.
Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r-- | src/drivers/intel/fsp1_1/Makefile.inc | 3 | ||||
-rw-r--r-- | src/drivers/intel/fsp1_1/stage_cache.c | 28 |
2 files changed, 0 insertions, 31 deletions
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 10877b9482..1372e98565 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c @@ -37,13 +36,11 @@ ramstage-y += fsp_relocate.c ramstage-y += fsp_util.c ramstage-y += hob.c ramstage-y += ramstage.c -ramstage-y += stage_cache.c ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include -postcar-y += stage_cache.c ifneq ($(CONFIG_SKIP_FSP_CAR),y) postcar-y += temp_ram_exit.c postcar-y += exit_car.S diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c deleted file mode 100644 index ab0c1c0126..0000000000 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <stage_cache.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} |