diff options
| author | EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> | 2022-10-03 16:24:04 +0800 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-11-09 22:35:27 +0000 |
| commit | 065c5870e4678367f5be7014361772c9d03933c8 (patch) | |
| tree | 42550d0b1a14f67fea6ce38536c0a8bcdada9452 /src/device/pci_rom.c | |
| parent | 7b73e85283bea7f456ab2f86ed1d1099eb88bc2f (diff) | |
ec/google/chromec: Expand EC share memory for DTTS
DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pci_rom.c')
0 files changed, 0 insertions, 0 deletions