diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-08-21 11:09:14 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-24 09:24:20 +0000 |
| commit | d234484f31e22b9d14bf37b3f9c0f9f6cb4533c5 (patch) | |
| tree | 4b52df8a6dec29884a7a88258c19e13ecb6c6101 /src/device/pci_class.c | |
| parent | ae096be00c3ada5acc6dfd601a1ad2bb36e234db (diff) | |
mb/google/volteer/var/halvor: Correct USB device tree setting
Halvor uses TBT 0/1/2 for USB type C. We doesn't use PCIE/USB3 port
therefore disable PCIE/USB3 ports and enable TBT 2.
Follow volteer to set USB2 OC_SKIP.
BUG=b:165175296
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifb844ce475f3d58f0c95be0f172fc49edb4cd5fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/device/pci_class.c')
0 files changed, 0 insertions, 0 deletions