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authorWisley Chen <wisley.chen@quanta.corp-partner.google.com>2020-04-21 17:48:10 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-04-27 16:13:07 +0000
commit2f7f0c62fdacde2b7960c58f8608066f23a8c79b (patch)
tree93603a4938580282b020b7f66ed71e4509cf0c52 /src/device/i2c.c
parent2f58a007a7528090454d3384bacc973c503b4d20 (diff)
mb/google/hatch/var/jinlon: Update DPTF parameters
The change applies the DPTF parameters received from the thermal team. 1. Set PL1 Min to 3W 2. Set sample period of TCPU/TSR0/TSR1 to 30 Sec 3. Enable EC_ENABLE_MULTIPLE_DPTF_PROFILES and add trigger points for tablet mode. 4. Update trigger points of CPU/TSR0/TSR1 BUG=b:154564062, b:154290855 BRANCH=hatch TEST=build and verified by thermal team. Change-Id: I87170e63de222487a3bda1217c4ee87a2ec1984f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/device/i2c.c')
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