src/cpu/intel: Set get_ia32_fsb function common

Add get_ia32_fsb returns FSB values in MHz of intel's CPUs.
Also add get_ia32_fsb_x3 function. It returns round up 3 * get_ia32_fsb.

Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30103
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 96 insertions, 46 deletions

diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
index 1e94ec92e4..b67ca85f0e 100644
--- a/src/cpu/intel/common/Makefile.inc
+++ b/src/cpu/intel/common/Makefile.inc
@@ -1 +1,5 @@
 ramstage-y += common_init.c
+romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
+ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
+postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
new file mode 100644
index 0000000000..1f7c391a8f
--- /dev/null
+++ b/src/cpu/intel/common/fsb.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/fsb.h>
+#include <console/console.h>
+#include <commonlib/helpers.h>
+
+int get_ia32_fsb(void)
+{
+	struct cpuinfo_x86 c;
+	static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
+	static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
+	static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
+	msr_t msr;
+	int ret = -2;
+
+	get_fms(&c, cpuid_eax(1));
+	switch (c.x86) {
+	case 0x6:
+		switch (c.x86_model) {
+		case 0xe:  /* Core Solo/Duo */
+		case 0x1c: /* Atom */
+			ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+			break;
+		case 0xf:  /* Core 2 or Xeon */
+		case 0x17: /* Enhanced Core */
+			ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
+			break;
+		case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+		case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
+		case 0x3c: /* Haswell BCLK fixed at 100MHz */
+		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
+			ret = 100;
+			break;
+		}
+		break;
+	case 0xf: /* Netburst */
+		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
+		switch (c.x86_model) {
+		case 0x2:
+			ret = f2x_fsb[(msr.lo >> 16) & 7];
+			break;
+		case 0x3:
+		case 0x4:
+		case 0x6:
+			ret = core2_fsb[(msr.lo >> 16) & 7];
+			break;
+		}
+	}
+	if (ret == -1)
+		printk(BIOS_ERR, "FSB not found\n");
+	if (ret == -2)
+		printk(BIOS_ERR, "CPU not supported\n");
+	return ret;
+}
+
+/**
+ * @brief Returns three times the FSB clock in MHz
+ *
+ * The result of calculations with the returned value shall be divided by 3.
+ * This helps to avoid rounding errors.
+ */
+int get_ia32_fsb_x3(void)
+{
+	const int fsb = get_ia32_fsb();
+
+	if (fsb > 0)
+		return 100 * DIV_ROUND_CLOSEST(3 * fsb, 100);
+
+	printk(BIOS_ERR, "FSB not supported or not found\n");
+	return -1;
+}
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index e6a12ce387..b3ddeac17e 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <arch/cpu.h>
 #include <arch/early_variables.h>
+#include <cpu/intel/fsb.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
@@ -44,53 +45,13 @@ static u32 g_timer_fsb CAR_GLOBAL;
 
 static int set_timer_fsb(void)
 {
-	struct cpuinfo_x86 c;
-	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
-	int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
-	int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 };
-	msr_t msr;
-
-	get_fms(&c, cpuid_eax(1));
-	switch (c.x86) {
-	case 0x6:
-		switch (c.x86_model) {
-		case 0xe:  /* Core Solo/Duo */
-		case 0x1c: /* Atom */
-			car_set_var(g_timer_fsb,
-				core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
-			return 0;
-		case 0xf:  /* Core 2 or Xeon */
-		case 0x17: /* Enhanced Core */
-			car_set_var(g_timer_fsb,
-				core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
-			return 0;
-		case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
-		case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
-		case 0x3c: /* Haswell BCLK fixed at 100MHz */
-		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
-			car_set_var(g_timer_fsb, 100);
-			return 0;
-		default:
-			car_set_var(g_timer_fsb, 200);
-			return 0;
-		}
-	case 0xf: /* Netburst */
-		msr = rdmsr(MSR_EBC_FREQUENCY_ID);
-		switch (c.x86_model) {
-		case 0x2:
-			car_set_var(g_timer_fsb,
-				f2x_fsb[(msr.lo >> 16) & 7]);
-			return 0;
-		case 0x3:
-		case 0x4:
-		case 0x6:
-			car_set_var(g_timer_fsb,
-				core2_fsb[(msr.lo >> 16) & 7]);
-			return 0;
-		}  /* default: fallthrough */
-	default:
-		return -1;
+	int ia32_fsb = get_ia32_fsb();
+
+	if (ia32_fsb > 0) {
+		car_set_var(g_timer_fsb, ia32_fsb);
+		return 0;
 	}
+	return -1;
 }
 
 static inline u32 get_timer_fsb(void)