- Actually enable the Pentium-M cpus

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 0 insertions, 4 deletions

diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index 43c1f252a7..600ad46418 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -37,9 +37,7 @@ static struct device_operations cpu_dev_ops = {
 	.init     = model_69x_init,
 };
 static struct cpu_device_id cpu_table[] = {
-#if 0
 	{ X86_VENDOR_INTEL, 0x0695 }, /* Pentium M */
-#endif
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index b646066eb6..ca00df43b4 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -37,9 +37,7 @@ static struct device_operations cpu_dev_ops = {
 	.init     = model_6dx_init,
 };
 static struct cpu_device_id cpu_table[] = {
-#if 0
 	{ X86_VENDOR_INTEL, 0x06D6 }, /* Pentium M on 90nm with 2MiB of L2 cache */
-#endif
 	{ 0, 0 },
 };