diff options
| author | Marc Jones <marcj303@gmail.com> | 2009-06-16 23:02:39 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2009-06-16 23:02:39 +0000 |
| commit | cbefc238c53ad5fbfa03b734e9dcd3dd50c00f40 (patch) | |
| tree | 5ff2b4c80199e0fc0b1741834e129751d9adf805 /src/cpu | |
| parent | d41de2ea7a65242f5c95e578d99cf46cd23920dd (diff) | |
Maximilian Thuermer found a bug where the HT link capability code was always
updating the passed value to the next link offset even when it was on the
requested link (cap_count).
Maximilian also found a bug where the linktype was still getting attributes
even when it wasn't initialized.
This should fix the HT problems for Fam10 C2. There are still issues with the
microcode which need to be resolved.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 37 |
1 files changed, 20 insertions, 17 deletions
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 2b08b61791..92eb2de0c8 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -719,11 +719,13 @@ BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) do { val = pci_read_config32(NODE_PCI(node, 0), val); /* Is the capability block a HyperTransport capability block? */ - if ((val & 0xFF) == 0x08) + if ((val & 0xFF) == 0x08) { /* Is the HT capability block an HT Host Capability? */ if ((val & 0xE0000000) == (1 << 29)) cap_count--; - val = (val >> 8) & 0xFF; + } + if (cap_count) + val = (val >> 8) & 0xFF; } while (cap_count && val); *offset = (u8) val; @@ -745,9 +747,9 @@ BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) u32 AMD_checkLinkType (u8 node, u8 link, u8 regoff) { u32 val; - u32 linktype; + u32 linktype = 0; - /* Check coherency */ + /* Check connect, init and coherency */ val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18); val &= 0x1F; @@ -757,23 +759,24 @@ u32 AMD_checkLinkType (u8 node, u8 link, u8 regoff) if (val == 7) linktype |= HTPHY_LINKTYPE_NONCOHERENT; - /* Check gen3 */ - val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08); + if (linktype) { + /* Check gen3 */ + val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08); - if (((val >> 8) & 0x0F) > 6) - linktype |= HTPHY_LINKTYPE_HT3; - else - linktype |= HTPHY_LINKTYPE_HT1; + if (((val >> 8) & 0x0F) > 6) + linktype |= HTPHY_LINKTYPE_HT3; + else + linktype |= HTPHY_LINKTYPE_HT1; - /* Check ganged */ - val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170); - - if ( val & 1) - linktype |= HTPHY_LINKTYPE_GANGED; - else - linktype |= HTPHY_LINKTYPE_UNGANGED; + /* Check ganged */ + val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170); + if ( val & 1) + linktype |= HTPHY_LINKTYPE_GANGED; + else + linktype |= HTPHY_LINKTYPE_UNGANGED; + } return linktype; } |