coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

17 files changed, 51 insertions, 51 deletions

diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 2a9f8c55e9..9e00c55a92 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -29,8 +29,8 @@
 
 #include <arch/rom_segs.h>
 
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \
-    IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \
+    CONFIG(SIPI_VECTOR_IN_ROM)
 /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
  * Startup IPI message without RAM.
  */
@@ -44,7 +44,7 @@ _start16bit:
 	cli
 	/* Save the BIST result */
 	movl	%eax, %ebp
-#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
+#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
 	post_code(POST_RESET_VECTOR_CORRECT)
 #endif
 
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 837bccf87a..52c07685cf 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -47,7 +47,7 @@ __protected_start:
 	/* Save the BIST value */
 	movl	%eax, %ebp
 
-#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
+#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
 	post_code(POST_ENTER_PROTECTED_MODE)
 #endif
 
diff --git a/src/cpu/x86/backup_default_smm.c b/src/cpu/x86/backup_default_smm.c
index 2023aede74..7b982a629e 100644
--- a/src/cpu/x86/backup_default_smm.c
+++ b/src/cpu/x86/backup_default_smm.c
@@ -25,7 +25,7 @@ void *backup_default_smm_area(void)
 	void *save_area;
 	const void *default_smm = (void *)SMM_DEFAULT_BASE;
 
-	if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+	if (!CONFIG(HAVE_ACPI_RESUME))
 		return NULL;
 
 	/*
diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c
index 1a99c36d82..6fc61686df 100644
--- a/src/cpu/x86/car.c
+++ b/src/cpu/x86/car.c
@@ -20,7 +20,7 @@
 #include <arch/early_variables.h>
 #include <symbols.h>
 
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
+#if CONFIG(PLATFORM_USES_FSP1_0)
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #endif
 typedef void (* const car_migration_func_t)(void);
@@ -61,7 +61,7 @@ void *car_get_var_ptr(void *var)
 		return var;
 	}
 
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
+#if CONFIG(PLATFORM_USES_FSP1_0)
 	migrated_base = (char *)find_saved_temp_mem(
 			*(void **)CBMEM_FSP_HOB_PTR);
 	/* FSP 1.0 migrates the entire DCACHE RAM */
@@ -96,7 +96,7 @@ void *car_sync_var_ptr(void *var)
 	 * keep console buffer in CAR until cbmemc_reinit() moves it.
 	 */
 	if (*mig_var == _preram_cbmem_console) {
-		if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
+		if (CONFIG(PLATFORM_USES_FSP1_0))
 			*mig_var += (char *)mig_var - (char *)var;
 		return mig_var;
 	}
@@ -142,7 +142,7 @@ static void do_car_migrate_variables(void)
 
 static void car_migrate_variables(int is_recovery)
 {
-	if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
+	if (!CONFIG(PLATFORM_USES_FSP1_0))
 		do_car_migrate_variables();
 }
 ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables)
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index ea10fd0554..6521a8a308 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -98,7 +98,7 @@ void udelay(u32 usecs)
 	} while ((start - value) < ticks);
 }
 
-#if IS_ENABLED(CONFIG_LAPIC_MONOTONIC_TIMER)
+#if CONFIG(LAPIC_MONOTONIC_TIMER)
 #include <timer.h>
 
 static struct monotonic_counter {
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 4654086114..f4c2326a0b 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -15,7 +15,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic_def.h>
 
-#if IS_ENABLED(CONFIG_SMP)
+#if CONFIG(SMP)
 int boot_cpu(void)
 {
 	int bsp;
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 7daca0ac67..3ad1f0a055 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -147,9 +147,9 @@ static int lapic_start_cpu(unsigned long apicid)
 		}
 		return 0;
 	}
-#if !IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) \
-	&& !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_206AX) \
-	&& !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_2065X)
+#if !CONFIG(CPU_AMD_MODEL_10XXX) \
+	&& !CONFIG(CPU_INTEL_MODEL_206AX) \
+	&& !CONFIG(CPU_INTEL_MODEL_2065X)
 	mdelay(10);
 #endif
 
@@ -320,7 +320,7 @@ int start_cpu(struct device *cpu)
 	return result;
 }
 
-#if IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT)
+#if CONFIG(AP_IN_SIPI_WAIT)
 
 /**
  * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of
@@ -408,7 +408,7 @@ asmlinkage void secondary_cpu_init(unsigned int index)
 {
 	atomic_inc(&active_cpus);
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+	if (!CONFIG(PARALLEL_CPU_INIT))
 		spin_lock(&start_cpu_lock);
 
 #ifdef __SSE3__
@@ -423,7 +423,7 @@ asmlinkage void secondary_cpu_init(unsigned int index)
 #endif
 	cpu_initialize(index);
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+	if (!CONFIG(PARALLEL_CPU_INIT))
 		spin_unlock(&start_cpu_lock);
 
 	atomic_dec(&active_cpus);
@@ -440,7 +440,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
 		if (cpu->path.type != DEVICE_PATH_APIC)
 			continue;
 
-		if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
+		if (CONFIG(PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
 			continue;
 
 		if (!cpu->enabled)
@@ -454,7 +454,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
 			printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
 				cpu->path.apic.apic_id);
 
-		if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+		if (!CONFIG(PARALLEL_CPU_INIT))
 			udelay(10);
 	}
 
@@ -554,24 +554,24 @@ void initialize_cpus(struct bus *cpu_bus)
 	if (is_smp_boot())
 		copy_secondary_start_to_lowest_1M();
 
-	if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
+	if (!CONFIG(SERIALIZED_SMM_INITIALIZATION))
 		smm_init();
 
 	/* start all aps at first, so we can init ECC all together */
-	if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+	if (is_smp_boot() && CONFIG(PARALLEL_CPU_INIT))
 		start_other_cpus(cpu_bus, info->cpu);
 
 	/* Initialize the bootstrap processor */
 	cpu_initialize(0);
 
-	if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+	if (is_smp_boot() && !CONFIG(PARALLEL_CPU_INIT))
 		start_other_cpus(cpu_bus, info->cpu);
 
 	/* Now wait the rest of the cpus stop*/
 	if (is_smp_boot())
 		wait_other_cpus_stop(cpu_bus);
 
-	if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) {
+	if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) {
 		/* At this point, all APs are sleeping:
 		 * smm_init() will queue a pending SMI on all cpus
 		 * and smm_other_cpus() will start them one by one */
@@ -589,7 +589,7 @@ void initialize_cpus(struct bus *cpu_bus)
 		recover_lowest_1M();
 }
 
-#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if !CONFIG(HAVE_SMI_HANDLER)
 /* Empty stubs for platforms without SMI handlers. */
 void smm_init(void)
 {
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 3889c7d28e..2057df011f 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -714,7 +714,7 @@ struct mp_state {
 
 static int is_smm_enabled(void)
 {
-	return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && mp_state.do_smm;
+	return CONFIG(HAVE_SMI_HANDLER) && mp_state.do_smm;
 }
 
 static void smm_disable(void)
@@ -724,7 +724,7 @@ static void smm_disable(void)
 
 static void smm_enable(void)
 {
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
+	if (CONFIG(HAVE_SMI_HANDLER))
 		mp_state.do_smm = 1;
 }
 
@@ -891,7 +891,7 @@ static int run_ap_work(struct mp_callback *val, long expire_us)
 	struct stopwatch sw;
 	int cur_cpu = cpu_index();
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) {
+	if (!CONFIG(PARALLEL_MP_AP_WORK)) {
 		printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n");
 		return -1;
 	}
@@ -933,7 +933,7 @@ static void ap_wait_for_instruction(void)
 	struct mp_callback **per_cpu_slot;
 	int cur_cpu;
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK))
+	if (!CONFIG(PARALLEL_MP_AP_WORK))
 		return;
 
 	cur_cpu = cpu_index();
@@ -1028,7 +1028,7 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
 	 * Default to smm_initiate_relocation() if trigger callback isn't
 	 * provided.
 	 */
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) &&
+	if (CONFIG(HAVE_SMI_HANDLER) &&
 		ops->per_cpu_smm_trigger == NULL)
 		mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation;
 }
diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c
index c562d84941..c430bc1e8f 100644
--- a/src/cpu/x86/mtrr/debug.c
+++ b/src/cpu/x86/mtrr/debug.c
@@ -197,6 +197,6 @@ static void _display_mtrrs(void)
 
 asmlinkage void display_mtrrs(void)
 {
-	if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
+	if (CONFIG(DISPLAY_MTRRS))
 		_display_mtrrs();
 }
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index b45d17f010..d87c3d43d3 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,7 @@
 #include <memrange.h>
 #include <cpu/amd/mtrr.h>
 #include <assert.h>
-#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
+#if CONFIG(X86_AMD_FIXED_MTRRS)
 #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM)
 #else
 #define MTRR_FIXED_WRBACK_BITS 0
@@ -86,7 +86,7 @@ void fixed_mtrrs_expose_amd_rwdram(void)
 {
 	msr_t syscfg;
 
-	if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS))
+	if (!CONFIG(X86_AMD_FIXED_MTRRS))
 		return;
 
 	syscfg = rdmsr(SYSCFG_MSR);
@@ -98,7 +98,7 @@ void fixed_mtrrs_hide_amd_rwdram(void)
 {
 	msr_t syscfg;
 
-	if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS))
+	if (!CONFIG(X86_AMD_FIXED_MTRRS))
 		return;
 
 	syscfg = rdmsr(SYSCFG_MSR);
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index a7e4522943..11f0c2476a 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -172,7 +172,7 @@ microcode_done:
 	test	%ebx, %ebx
 	jz	1f
 
-#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
+#if CONFIG(X86_AMD_FIXED_MTRRS)
 	/* Allow modification of RdDram and WrDram bits */
 	mov	$SYSCFG_MSR, %ecx
 	rdmsr
@@ -189,7 +189,7 @@ load_msr:
 	dec	%ebx
 	jnz	load_msr
 
-#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
+#if CONFIG(X86_AMD_FIXED_MTRRS)
 	mov	$SYSCFG_MSR, %ecx
 	rdmsr
 	and	$~SYSCFG_MSR_MtrrFixDramModEn, %eax
@@ -202,7 +202,7 @@ load_msr:
 	and	$~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax
 	mov	%eax, %cr0
 
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
 	/* Enable sse instructions. */
 	mov	%cr4, %eax
 	orl	$(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index 8c65cbd828..0ffa46537c 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -19,7 +19,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
 #include <spi-generic.h>
 #endif
 
@@ -186,7 +186,7 @@ void smi_handler(u32 smm_revision)
 
 	/* Allow drivers to initialize variables in SMM context. */
 	if (do_driver_init) {
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
 		spi_init();
 #endif
 		do_driver_init = 0;
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index f9af965208..0d9abc5763 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -18,7 +18,7 @@
 #include <cpu/x86/smm.h>
 #include <rmodule.h>
 
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
 #include <spi-generic.h>
 #endif
 
@@ -161,7 +161,7 @@ asmlinkage void smm_handler_start(void *arg)
 
 	/* Allow drivers to initialize variables in SMM context. */
 	if (do_driver_init) {
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
 		spi_init();
 #endif
 		do_driver_init = 0;
@@ -180,7 +180,7 @@ asmlinkage void smm_handler_start(void *arg)
 		       expected_canary);
 
 		// Don't die if we can't indicate an error.
-		if (IS_ENABLED(CONFIG_DEBUG_SMI))
+		if (CONFIG(DEBUG_SMI))
 			die("SMM Handler caused a stack overflow\n");
 	}
 
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index 6c166454dc..80b2c27c79 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -346,7 +346,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
 		return -1;
 
 	/* Clear SMM region */
-	if (IS_ENABLED(CONFIG_DEBUG_SMI))
+	if (CONFIG(DEBUG_SMI))
 		memset(smram, 0xcd, size);
 
 	total_stack_size = params->per_cpu_stack_size *
@@ -370,7 +370,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
 		base += alignment_size;
 	}
 
-	if (IS_ENABLED(CONFIG_SSE)) {
+	if (CONFIG(SSE)) {
 		fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks;
 		/* FXSAVE area below all the stacks stack. */
 		fxsave_area = params->stack_top;
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 06c7fa4e7f..f586b35154 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -77,7 +77,7 @@
 #endif
 .global smm_handler_start
 smm_handler_start:
-#if IS_ENABLED(CONFIG_SMM_LAPIC_REMAP_MITIGATION)
+#if CONFIG(SMM_LAPIC_REMAP_MITIGATION)
 	/* Check if the LAPIC register block overlaps with SMM.
 	 * This block needs to work without data accesses because they
 	 * may be routed into the LAPIC register block.
@@ -139,7 +139,7 @@ untampered_lapic:
 	/* This is an ugly hack, and we should find a way to read the CPU index
 	 * without relying on the LAPIC ID.
 	 */
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
+#if CONFIG(CPU_AMD_AGESA_FAMILY15_TN)
 	/* LAPIC IDs start from 0x10; map that to the proper core index */
 	subl	$0x10, %ecx
 #endif
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index fa49def1ad..c282904de9 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -21,9 +21,9 @@
 // can it be cleaned up so this include is not required?
 // It's needed right now because we get our DEFAULT_PMBASE from
 // here.
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
+#if CONFIG(SOUTHBRIDGE_INTEL_I82801DX)
 #include <southbridge/intel/i82801dx/i82801dx.h>
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)
+#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX)
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #else
 #error "Southbridge needs SMM handler support."
@@ -32,7 +32,7 @@
 // ADDR32() macro
 #include <arch/registers.h>
 
-#if IS_ENABLED(CONFIG_SMM_TSEG)
+#if CONFIG(SMM_TSEG)
 #error "Don't use this file with TSEG."
 
 #endif /* CONFIG_SMM_TSEG */
@@ -154,7 +154,7 @@ smm_relocate:
 
 	/* End of southbridge specific section. */
 
-#if IS_ENABLED(CONFIG_DEBUG_SMM_RELOCATION)
+#if CONFIG(DEBUG_SMM_RELOCATION)
 	/* print [SMM-x] so we can determine if CPUx went to SMM */
 	movw $CONFIG_TTYS0_BASE, %dx
 	mov $'[', %al
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index a589cdb8dd..0784822b30 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -98,7 +98,7 @@ bad_ctc:
 
 static unsigned long calibrate_tsc(void)
 {
-	if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+	if (CONFIG(TSC_CONSTANT_RATE))
 		return tsc_freq_mhz();
 	else
 		return calibrate_tsc_with_pit();
@@ -135,7 +135,7 @@ void udelay(unsigned int us)
 	}
 }
 
-#if IS_ENABLED(CONFIG_TSC_MONOTONIC_TIMER)
+#if CONFIG(TSC_MONOTONIC_TIMER)
 #include <timer.h>
 
 static struct monotonic_counter {