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author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-20 14:08:32 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-21 15:48:13 +0000 |
commit | 69ababcbf61915456888a480f9d73b67e47e4a84 (patch) | |
tree | 9df78b8dac0dec20d829ad446ca9666fa9afd3cc /src/cpu/x86/Kconfig.debug_cpu | |
parent | cc827d9aab1f0ef25a77ebc64755cf4454857f4b (diff) |
cpu/amd/pi/00730F01/fixme: use coreboot's PCI access functions
Use coreboot's native PCI access functions instead of using the
vendorcode's PCI access functions to set up the CPU IO routing in
function 1 of the HT PCI device. This file still has room for
improvement, but at least it's now using coreboot-native functionality.
Stoneyridge has a nicer implementation, but looking into possibly
unifying those is out of scope for this patch.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieecc0e5f6576a838d79220b061de81e21b5d976c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/cpu/x86/Kconfig.debug_cpu')
0 files changed, 0 insertions, 0 deletions