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authorSubrata Banik <subrata.banik@intel.com>2017-08-16 18:38:54 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-26 06:03:00 +0000
commit97a09454d25bc19b80ae990743602ba0f943a9c0 (patch)
treebc00fd1beb7fe7800448195ae9943cf6a33a5951 /src/cpu/ti
parentf61ffcf9a489fa5d971f8584450be0869e6ca78d (diff)
soc/intel/skylake: Move DMI lock down config after resource allocation
This patch to ensures that coreboot is performing DMI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence BIOS Interface lock down through Sideband access has been moved right after pci resource allocation is done, so that BILD lock down is getting executed along with LPC and SPI BIOS interface lockdown settings before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure DMI register offset 0x274c bit 0 is set. Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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