diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2014-10-30 14:49:53 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-02 21:46:13 +0200 |
| commit | 33c10f8c32a16701ad601d491322fb2468111b9b (patch) | |
| tree | 52bb85a8b1d3a58eaf321f193032b11caf315d01 /src/cpu/mips | |
| parent | b92e54333f75baa86bcda67b1beeb19669250f03 (diff) | |
urara: Configure UART line control to 8N1
8bit, 1 stop bit, no parity
BUG=chrome-os-partner:31438
TEST=built urara bootblock and ran it on the Pistachio FPGA, observed
expected console output.
BRANCH=none
Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e
Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226551
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9185
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/mips')
0 files changed, 0 insertions, 0 deletions