diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2024-02-02 18:49:53 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-03-28 15:22:34 +0000 |
| commit | ee83be4d753ae128b53dd306b380c4a6dfd739e5 (patch) | |
| tree | a22c88456df0343f37e7dbaf35627857ae6d9fb8 /src/cpu/intel | |
| parent | 34684caad56a489b26c0cf7f5f7f98cff7dc72c5 (diff) | |
cpu/x86: Link page tables in stage if possible
When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.
The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
not overlap.
- Works with non memory mapped flash (however all coreboot targets
currently do support this)
- If later stages can use their own page tables which fits better with
the vboot RO/RW flow
A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.
Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.
TEST: Booted to payload on google/vilbox and qemu/q35
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/car/core2/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/cpu/intel/car/non-evict/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 2e4d9c8074..227ddf4c22 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -163,7 +163,7 @@ addrsize_set_high: subl $4, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 578bf03afd..9485cd44fb 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -214,7 +214,7 @@ end_microcode_update: andl $0xfffffff0, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 32fddd6810..1cb422dbfc 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -363,7 +363,7 @@ fill_cache: subl $4, %esp #if ENV_X86_64 - setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC) + setup_longmode $PM4LE movd %mm2, %rdi shlq $32, %rdi /* BIST */ |