diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-09-11 13:32:14 +0200 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-09-20 07:51:20 +0000 |
| commit | 1caa27932585d809fb3c76384ac32b632db5fdec (patch) | |
| tree | 94bfb0345986ddeeca2e4823f3e8eeac07786c29 /src/cpu/intel | |
| parent | 0d3606b2df7dc2625c14f981821ab3f09d696065 (diff) | |
cpu/intel/haswell: Do not include useless µcode updates
There are two types of Haswell/Broadwell platforms: Trad(itional) with
separate CPU and PCH packages, and ULT/ULX where the CPU and PCH share
one package. Mainboards can specify which platform type they are using
the `INTEL_LYNXPOINT_LP` Kconfig option. There are so many differences
between Trad and ULT/ULX that it's not worth doing runtime detection.
The CPUIDs are different for Trad and ULT/ULX platforms, and so are the
µcode updates. So, including Trad µcode updates in a coreboot image for
an ULT/ULX mainboard makes no sense, and vice versa.
Adapt the Makefile so that only relevant µcode updates are added. Also,
add a few comments to indicate which updates correspond to which CPUs.
TEST=Run binwalk on coreboot.rom to verify included µcode updates for:
- Asrock B85M Pro4 (Haswell Trad)
- HP Folio 9480M (Haswell ULT/ULX)
- Purism Librem BDW (Broadwell ULT/ULX)
Change-Id: I6dc9e94ce9fede15cbcbe6be577c48c197a9212a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index b425efd5d6..19b268e2ef 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -18,9 +18,14 @@ postcar-y += ../car/non-evict/exit_car.S subdirs-y += ../microcode subdirs-y += ../turbo -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) +ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +# Haswell ULT/ULX cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) - ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +# Broadwell ULT/ULX cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin endif +else +# Haswell Trad +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) +endif |