diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-10-07 18:24:58 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-10-22 16:39:05 +0000 |
| commit | 436f1c471a576d36101d7ef42e29d2c4e28950e6 (patch) | |
| tree | 3354b40e1b314d5a8aeeeef06efd3e2309c4e12b /src/cpu/intel/socket_LGA775 | |
| parent | 036b16b884725c044c82724c005b823a8663c970 (diff) | |
mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.
However, we need the root ports accessible before FspMemoryInit() in
certain cases, such as emitting POST codes through a PCIe device.
For the initialization to happen properly, certain register writes
specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter
3.3.1 have to be done.
BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().
Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/socket_LGA775')
0 files changed, 0 insertions, 0 deletions