diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2022-02-02 18:34:58 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-07-17 18:57:54 +0000 |
| commit | 6c42fa20f60456dce677674d6a91c542ab00faa7 (patch) | |
| tree | e82188c72b791d6de63da94ccd3642c3dbd72be7 /src/cpu/intel/slot_1 | |
| parent | f5517848308f93b53dd28c1e8ffed40709074a86 (diff) | |
cpu: Get rid of unnecessary blank line {before,after} barce
Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/cpu/intel/slot_1')
| -rw-r--r-- | src/cpu/intel/slot_1/l2_cache.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index 2a273168f3..fa433660b6 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -244,7 +244,6 @@ int read_l2(u32 address) /* If OK then get the result from BBL_CR_ADDR */ msr = rdmsr(BBL_CR_ADDR); return (msr.lo >> 0x15); - } /* Write data into the L2 controller register at address */ @@ -270,7 +269,6 @@ int write_l2(u32 address, u32 data) */ for (i = 0; i < v2; i++) { - u32 data1, data2; // Bits legend // data1 = ffffffff @@ -352,7 +350,6 @@ int calculate_l2_cache_size(void) */ for (cache_setting = BBLCR3_L2_SIZE_256K; cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) { - eax = bblcr3 | cache_setting; msr.lo = eax; wrmsr(BBL_CR_CTL3, msr); @@ -726,7 +723,6 @@ int p6_configure_l2_cache(void) /* Write to all cache lines to initialize */ while (cache_size > 0) { - /* Each cache line is 32 bytes. */ cache_size -= 32; |