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authorRaul E Rangel <rrangel@chromium.org>2021-02-10 16:36:33 -0700
committerMartin Roth <martinroth@google.com>2021-02-12 20:44:48 +0000
commit0f3bc81210f364a6e96edd090d9310844aa30aa2 (patch)
tree98ed030848ddb46c2cf03cdd7b221d1c7fc153d9 /src/cpu/intel/model_6ex
parent48c99db6d6af3bf642866646b915bc5a57dcb4a5 (diff)
soc/amd: Move southbridge_write_acpi_tables
This is common between all the chipsets. It's also required by common/block/lpc/lpc.c. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_6ex')
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